Sujay Subramanian
@sujay_subbu16
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Work Experience
Graduate Researcher
University of Illinois Urbana-Champaign•  December 2024 - Present
Design and modeling of component-level ESD protection for IO signal pins.
ASIC Intern
NVIDIA Corporation, Bangalore•  July 2023 - December 2023•  Bangalore
Designed and maintained SPICE simulation tools, performed data extraction and analysis to track trends in 3 different special-purpose ring oscillators across PVT, VT type, and BSIM parameter variations. Developed Python-based automation scripts, decreasing execution time from 5 hours to 10 min, to run Dynamic Circuit Checks, which helped identify design bugs early in the development cycle and reduce potential downstream issues. Simulated the RO circuits in TSMC3 and TSMC5 technology, observing a 40% higher operating frequency in the 3nm process.
Research Intern
CSIR-CEERI, Pilani•  May 2022 - July 2022•  Pilani
Designed and simulated a novel PZT-based PMUT sensor on COMSOL, achieving a resonance frequency of 6.6781 MHz. Performed parametric studies showing that radius inversely impacted frequency, while thickness showed a direct relation.
Education
University of Illinois Urbana-Champaign
Master of Science in Electrical and Computer Engineering•  August 2024 - Present•  GPA: 3.85
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering in Electrical and Electronics•  November 2020 - May 2024•  GPA: 9.3
