Siddhartha -

Machine Learning Engineer

SAP Asia Pte Ltd•  June 2021 - Present

Part of the machine learning engineering team that focuses on building scalable and production-ready machine learning solutions for key internal stakeholders. I have gained additional experience in the following areas since joining the team: (1) Information retrieval system design with Elastic/Open-search, (2) Production-friendly practices, such as dockerization, CI/CD, poetry for python development, etc, (3) Agile scrum methodology for handling long-term software engineering projects.

Chief Technology Officer

Inpact Technologies Pte Ltd•  February 2020 - June 2021

inPact.ai provides state-of-the-art business intelligence software that (1) uses AI to extract key commercial terms from contracts, and (2) provides an integrated analytics platform that enables corporate departments to access business insights from their contract base not available from other systems of record. inPact.ai was incubated by Entrepreneur First (backed by SGInnovate) in Singapore. My role as the CTO and co-founder of the company included: (1) Leading all aspects of product development, including frontend, backend, deployment, and machine learning, (2) Hiring for technical positions; conducted interviews and hired two contractors and an intern to meet regular product development targets, (3) Hands-on product development experience with web technologies, including ReactJS, serverless framework, and AWS cloud infrastructure, (4) Handling business functions such as customer acquisition, corporate partnerships, investor relations, fundraising, marketing, and more.

Postdoctoral Research Associate

University of Sydney•  October 2017 - December 2019

Postdoctoral researcher in the Computer Engineering Lab (Electrical and Electronics Engineering) in the University of Sydney. Research questions asked during this period led to projects related to FPGA computing and its application to novel machine learning domains. Conducted research on: next-generation FPGA (overlay) architectures, low-precision deep neural networks, on-chip machine learning, and RF communication systems (Ettus RFNoC framework). One research project, funded by the Australian Defense Science & Technologies, explored FPGA-based implementations that achieve real-time spectral prediction on RF communication channels using modern deep learning methods and models. (Co-)Authored a total of 5 peer-reviewed research papers/posters during the stint. Supervised final year undergraduate projects, assisted with teaching/invigilation, and undertook sysadmin duties over lab resources.

Nanyang Technological University (NTU), Singapore

Computer Science & Engineering, PhD•  January 2013 - January 2019

Dissertation Title: Dataflow Overlays for FPGAs. Summary: This dissertation proposes a novel compute architecture - Dataflow Coprocessor Overlay (DaCO). DaCO is an FPGA-tuned dataflow-driven overlay architecture that offers fine-grained parallelism capable of delivering speedups of up to 2.8x on sparse, irregular computations over competing architectures (e.g. modern microprocessors and existing dataflow overlays). DaCO delivers these improvements with a custom instruction datapath that exploits the raw parallelism exposed by the dataflow triggering rule - instructions execute asynchronously as soon as their operands are available. However, this simple triggering logic can expose large amounts of irregular instruction-level parallelism that can be hard to manage. We address this challenge in three steps: (1) design of a lightweight scheduling circuit inside each DaCO soft-processor that enables large-scale out-of-order instruction execution at runtime (2) design of a priority-aware communication framework that delivers improved quality of service to critical communication packets, and (3) compiler support that optimizes the dataflow graph structure for improved runtime execution. DaCO is optimized for the Arria 10 AX115S (20nm SoC) FPGA board in order to take advantage of the hard on-chip floating-point DSP blocks. Overall, when benchmarked with sparse-matrix vector multiply kernels, DaCO improves throughput performance by up to 2.4x over existing in-order dataflow overlays, and delivers a peak operational throughput of up to 38 MFLOPs/processor, or peak total throughput of 3.5 GFLOPs/sec.