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Work Experience
Software Engineer
EATON•  September 2022 - Present
Firmware Engineer
Software Engineer
Continental component •  June 2018 - September 2022
Master in Embedded C, C++, Verilog, Linux, SystemC, UVM, SoC design, Yocto, SoC Bring-up, Micro-controller programming, Control System Design, RTOS Additional experience in Python, Perl, Tcl, and CAPL scripting. Summary : • Develop Linux IP’s for TI SoC. • SoC Bring-up using Yocto configuration/development. • Experience in RTL design and product development as a Design Engineer • Good understanding of ASIC design flow. • Experience in writing RTL modules and Test benches in Verilog HDL. • Good understanding of micro-architecture, logic optimization, synthesis, verification, Code coverage, and functional coverage. • Knowledge of Digital Logic Design, Verilog, System Verilog, and UVM. • Worked on assembly language programming for microcontroller.
Education
Shivaji University
Software Engineering, BE•  June 2012 - March 2015
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