Badges
Certifications
Work Experience
Applications Engineer
Synoptos Inc.• April 2017 - Present
RTL Design debugging. TCL, Perl, CSH, Bash script writing. Verilog, System Verilog, VHDL practices.
Verification Engineer
Wave• June 2015 - February 2016
RTL Design debug. Timing Analysis.
Education
University of Moratuwa, Sri Lanka
University of Moratuwa, Sri Lanka
Skills
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