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Work Experience
SOC Design Engineer
Intel Corporation•  August 2020 - Present•  Bangalore
Experienced Physical Design Engineer with Masters Degree in VLSI Design from Manipal Academy with expertise in Physical design, SI Sign-off Convergence, Methodology Automations, Backend flows & Tools. Skilled in RTL-GDSII flow, Complete SD Sign-off flow & TCL/Shell Automations. Worked on Multiple Server SOC's & Test chips in 22nm, 10nm & 7nm technology nodes.
Project Assistant
Aeronautical Development Agency•  August 2016 - August 2018•  Bangalore
Roles & Responsibilities include HSI Testing, Code Review, Functional testing And Analysis & Review of System, Software Requirements. Programming Language : Ada 95 Tools: Understand Ada
Education
Manipal Academy of Higher Education
VLSI Design, ME•  August 2019 - June 2021•  CGPA: 9.27
Sir M Visvesvaraya Institute of Technology
Electronics and Communication Engineering , BE•  September 2011 - July 2015•  Percentage: 77.69
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